Device and method for synchronizing an asynchronous signal in synthesis and simulation of a clocked circuit

ABSTRACT

An apparatus and a method for the synchronization of an asynchronous signal in synthesis and simulation of a clocked circuit are disclosed, in which a circuit to be simulated and tested is described with a hardware description language and the asynchronous signals present therein are marked. For producing a network list, the hardware description language is processed with a synthesis tool, in which a specific synchronization module is inserted at every marking. For testing the time behavior of the signals in the clocked circuit on the basis of the network list, a simulator implements a logic/timing simulation, in which a test of the time behavior is selectively deactivated for each inserted synchronization module. The unknown statusses that still occur are output via a display.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed to an apparatus and a method forsynchronization of an asynchronous signal in synthesis and simulation ofa clocked circuit and, in particular, to an apparatus and a method withwhich a critical condition can be separated from an uncritical conditionin the time behavior of a signal in a clocked circuit in theimplementation of a simulation.

2. Description of the Related Art

Application-specific integrated circuits (ASICs), customer-specificintegrated circuits (full-custom ICs) as well as their mixed forms(semi-custom ICs) are being increasingly tested for logical function andtime behavior in prior to manufacture by stimulation.

A circuit is usually described for stimulation in a hardware descriptionlanguage such as, a VHDL code, and the logical function of the circuitis tested with a VHDL logic simulator. A test of the time behavior ofthe signals, however, cannot be implemented with such a logic simulatoron the basis of the hardware description language (VHDL code).

For implementing a test of the time behavior of a circuit, the hardwaredescription language (VHDL code) must be converted by a synthesis toolinto a network list that represents a further code (circuit plan) of theoriginal circuit. On the basis of this network list, the time behaviorof the signals in the circuit can also be acquired or, tested with alogic/timing simulator.

Given such a test of the time behavior of the signals in the circuit or,respectively, timing simulation, time-critical signal statusses in thecircuit can have been recognized and eliminated in the simulation. Sucha signal status may be explained by way of example on the basis of aclocked flip-flop, but the invention is not limited to such componentparts.

FIG. 1 shows a circuit diagram of a traditional flip-flop FF1 with aninput terminal D, a clock input CLK and an output terminal Q. FIG. 2shows an exemplary signal-time behavior with which no time-criticalsignal status occurs in the clocked flip-flop FF1. Characteristicstypical of the component derive dependent on the technology employed or,respectively, on the technical realization of an electronic component(for example, a flip-flop) in a semiconductor. The characteristicscritical for the flip-flop FF1 according to FIG. 1 are the setup timet_(s) and the hold time t_(h). These times define a time span for theflip-flop FF1 shown in FIG. 1 before and after the leading edge of theclock signal CLK at which a dependable acceptance of a signal pending atthe input D ensues. Since, according to FIG. 2, the signal at the inputD already has a stable value “1” before the time span t_(s) and t_(h),the signal at the output Q of the flip-flop FF1 is dependably set to “1”at the time of the leading edge of the clock signal CLK.

In comparison, FIG. 3 shows a signal-time behavior with which aviolation of the setup time t_(s) occurs, for which reason the output Qassumes an undefined condition. According to FIG. 3, the leading edge ofthe signal at the input of the flip-flop FF1 falls into the time spant_(s) of the setup time, for which reason the signal at the output Qinitially proceeds into a metastable condition I in order to then assumean undefined but fixed condition II (“0” or “1”) after the time t_(m).The metastable condition has an approximate time durationt _(m)=5×t _(PD),where t_(PD) is the running time in the flip-flop FF1 from the clockinput CLK to the output Q. The time duration for t_(m) for themetastable condition I is dependent on the technology employed and onthe semiconductor employed. After the metastable condition I, in whichthe output signal Q usually oscillates, the output signal Q enters intoa stable but undefined condition II that is arbitrarily and randomlyassumed. The same is true for a violation of the hold time.

Such unknown, i.e., metastable or, undefined conditions in thesignal-time behavior are undesired since they disadvantageouslyinfluence the following circuit elements that interpret this signal andare generally referred to below as setup/hold time violations.

Particularly in the implementation of a logic/timing simulation test ofthe signal-time behavior of a clock circuit, the above-describedsetup/hold time violation has such an effect that the simulator outputsan “unknown” status for the affected signal, signals or circuit elementsthat are dependent on this affected signal circuit-oriented terms can nolonger be tested. This leads to considerable problems in a majority ofapplications (e.g., an abort of the simulation).

FIG. 4 shows a clock circuit that is composed of a first ASIC module A1and of a second ASIC module A2. The ASIC module A1 is operated with afirst clock signal CLKI, for example 16 MHz, and the ASIC module A2 isoperated with a second clock signal CLKII, for example 25 MHz. Theclocks CLKI and CLKII are not synchronized, resulting in the problemthat the ASIC module A1 outputs an output signal S_ASYNC that isasynchronous relative to the clock signal CLKII. The signal S_ASYNC isasynchronous relative to the input clock signal CLKII. Setup/hold timeviolations will occur in an input circuit of the ASIC module A2. For alogic/timing simulation of the circuit to be implemented according toFIG. 4, the entire ASIC module A2 thus can not be tested in view of itstime behavior since there is the potential risk of setup/hold timeviolations at the input FF of ASIC module A2. In order to avoid such anoutcome, the test of a setup/hold time violation can be generallydisabled or the signal curve of the respective signals is intentionallymodified for the implementation of the simulation; for example, thesignal S_ASYNC is generated synchronous with the clock CLKII. A furtherpossibility is to perform a manual intervention into the network list ofthe circuit to be simulated in order to selectively deactivate the testor, the setup time violation from the input circuit (flip-flop).

All of these measures, however, are time-consuming, susceptible toerror, or deteriorate the simulation result since the simulation is notbased on the real time behavior of the signals.

SUMMARY OF THE INVENTION

The invention is therefore based on the object of creating an apparatusand a method for synchronizing an asynchronous signal in synthesis andsimulation of a clocked circuit, by which the entire circuit can betested in a simple way with respect to setup/hold time violations.

This object is achieved by a method for the synchronization of anasynchronous signal in synthesis and simulation of a clocked circuit,comprising the steps of: a) describing the clocked circuit with a firstcode in a hardware description language; b) marking asynchronous signalsof the clocked circuit in the first code; c) implementing a synthesis ofthe first code for producing a second code in a network list format, andinserting a synchronization module at every marking; d) implementing alogic/timing simulation at the second code for testing time behavior ofsignals in the clocked circuit, and selectively deactivating the test ofthe time behavior for each inserted synchronization module by adaptationin a simulation model of the appertaining synchronization module; and e)displaying occurring, undefined signal-time behavior in the clockedcircuit.

This object is also achieved by an apparatus for detecting undefinedsignal-time behavior in a clocked circuit comprising: a) an input for afirst code describing a clocked circuit in a hardware descriptionlanguage; b) a first memory for storing the first code; c) a markingmechanism for marking asynchronous signals in the first code; d) asynthesis mechanism that produces a second code in a network list formatfrom the first code and stores this in a second memory, asynchronization module being inserted at every marking; e) a timingsimulator that implements a timing simulation at the second code fortesting time behavior of signals of the clocked circuit, the test of thetime behavior being selectively deactivated for each insertedsynchronization module by adaptation in a simulation model of anappertaining synchronization module; f) a display for displayingoccurring, undefined signal-time behavior; and g) a bus structure thatconnects the input, the first memory, the second memory, the markingmechanism, the display, the synthesis mechanism, and the timingsimulator to one another.

Inventively, thus a circuit is first described with a hardwaredescription language, and the existing asynchronous signals are marked.A synthesis of the hardware description subsequently takes place forproducing a network list, in which a synchronization module is insertedat every marking. A logic/timing simulation is implemented with thisnetwork list, in which the testing of the time behavior is deactivatedfor each inserted synchronization module. All further undefinedsignal-time behaviors that still occur are indicated.

Thus, clocked circuits having a plurality of signals that areasynchronous relative to one another can be completely tested in view oftheir time behavior without involved counter-measures for acquiringunavoidable but undefined statusses being required.

For example, an imaginary flip-flop can be inserted as synchronizationmodule, which comprises two series-connected flip-flops, in which asetup/hold time violation test for the first flip-flop is automaticallydeactivated in the implementation of the timing simulation.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in greater detail below on the basis ofexemplary embodiments with reference to the drawings.

FIG. 1 is a circuit diagram of a clocked flip-flop for illustratingsetup/hold time violations;

FIG. 2 is a circuit diagram illustrating the signal-time curves in theflip-flop according to FIG. 1, in which no unknown statusses occur;

FIG. 3 is a circuit diagram illustrating the signal-time curves in theflip-flop according to FIG. 1, in which unknown statusses occur;

FIG. 4 is a block circuit diagram of a clocked circuit with asynchronoussignals;

FIG. 5 is a block circuit diagram of a circuit for illustrating theconversion into a hardware description language;

FIG. 6 is a diagram illustrating the inventively generated network listfor the circuit according to FIG. 5;

FIG. 7 is a diagram illustrating the network list of a further exemplaryembodiment for the imaginary flip-flop according to FIG. 6;

FIG. 8 is a block circuit diagram with a logic causing a setup-timeviolation;

FIG. 9 is a timing diagram illustrating the signal-time curves of thecircuit according to FIG. 6;

FIG. 10 is a timing of diagram illustrating the signal-time curves ofthe circuit according to FIG. 8.

FIG. 11 is a flowchart of a method in accordance with the presentinvention; and

FIG. 12 is an apparatus implementing a method in accordance with thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 5 shows an illustration of a block circuit diagram for illustratingthe functioning of the inventively method. A circuit part A1 correspondsto the ASIC module A1 shown in FIG. 4, whereas a circuit part A2 in FIG.5 corresponds to the ASIC module A2 according to FIG. 4. The circuit isfirst described by a hardware description language. A frequentlyemployed hardware description language is the VHDL code, but differenthardware description languages can also be applied to the presentinvention. The circuit part A1 comprises an AND-gate AND and a clockedflip-flop FF1, and is described below in the VHDL code by way ofexample:

process A1 (CLKI)

begin

-   -   wait until (CLKI′ event and CLK=“1”);        C<=A & B;        end process;        process A21 (CLKI)        begin    -   wait until (CLKI′ event and CLKI=“b 1”);    -   S3<=S2;        end process;        process A22 (CLKII)        begin    -   wait until (CLKII′ event and CLKII=“1”);    -   S4<=S3;        end process;

The circuit part A1 and A2 according to FIG. 5 is described in view ofits logical function with this VHDL code. A logical test of the circuitcan be performed on the basis of this VHDL code with a VHDL logicsimulator.

As noted above, however, a timing simulation cannot be implemented onthe basis of this VHDL code. On the contrary, a network list that servesas the basis for the logic/timing simulation must be acquired bysynthesis from the hardware description language for the time analysisof the circuit according to FIG. 5.

A network list that essentially corresponds to the block circuit diagramaccording to FIG. 5 arises in the implementation of a traditionalsynthesis. Setup time violations can occur in the flip-flop FF2, sincethe flip-flop FF2 is supplied with a signal S2 that is not synchronousor, is asynchronous relative to the clock signal CLKII. Thus, themetastable or, undefined statusses shown in FIG. 3 can occur at theoutput Q of the flip-flop FF2 preventing testing of all of the followingcircuit regions in the circuit part A2.

FIG. 6 shows a block circuit diagram of a network list like thatgenerated with the inventive method or, apparatus.

First, all circuit components of the circuit according to FIG. 5 aredescribed in a hardware description language, in which all asynchronoussignals are marked in a suitable way (for example, ASYNC signal S2,etc.). The VHDL code created in this way is now checked with a VHDLlogic simulator in view of the logical functions of the circuitaccording to FIG. 5. A synthesis of the VHDL code subsequently takesplace for producing a network list, in which a synchronization module animaginary flip-flop IFF according to FIG. 6 is inserted for eachcorrespondingly marked asynchronous signal. This synchronization moduleserves for the synchronization of the asynchronous signal S2. Theremaining elements such as, the AND-gate ‘AND’ and the flip-flop FF1remain unmodified in the network list.

FIG. 9 illustrates the critical signal-time curves according to FIG. 5.CLKI references a clock signal that is input to a flip-flop FF1 at itsclock input. A signal S1 that derives from the AND operation of thesignals A and B is input at he input terminal D of the flip-flop FF1.The signal S2 shows the output signal of the flip-flop FF1 that issupplied to a flip-flop FF2 at its D-input as asynchronous signal S2(sync). According to FIG. 9, the signal S2 rises to the value “1” at thetime t₁ when the leading edge of the clock signal CLKI is adjacent atthe flip-flop FF1. Since the input signal S1 is already adjacent instable form for an adequately long time, no unknown statusses arise. Inthe same way, an output signal S3 of the flip-flop FF2 is set to thevalue “1” at time t₂ when the leading edge of a second clock signalCLKII is adjacent. In this case, too, no unknown signal statusses arisefor the signal S3, since the input signal of the flip-flop FF2 isalready adjacent in stable form for an adequately long time.

Due to the fact, however, that the clock signals CLKI and CLKII are notsynchronized with one another and, over and above this, exhibitdifferent clock frequencies, a setup time violation of the flip-flop 2can occur at time t₃. As shown in FIG. 9, namely, the leading edge ofthe clock signal CLKII that triggers the second flip-flop FF2 canessentially coincide with the trailing edge of the signal S2, so that nocompletely defined signal for the flip-flop FF2 is present in thecritical time span of the setup time.

As was already described on the basis of FIG. 3, such an unstablecondition initially produces a metastable condition with the timeduration t_(m) at the input terminal of a flip-flop, the output signalS3 oscillating during this time and then assuming an arbitrary,undefined but fixed status. This status at time t₃ is usuallyinterpreted as an unknown status, creating an unknown status for allsignals that depend on output signal S3.

According to the inventive method, however, an imaginary flip-flop IFF23(synchronization FF) according to FIG. 6 is inserted into the networklist at a marked, asynchronous signal in a circuit to be simulated.Setup/hold time violations are suppressed for this specific element in asuitable way (for example, with corresponding adaptations in thesimulation model of the IFF23), for which reason the output signal ofthe imaginary flip-flop IFF23 is a defined signal and causes no problemsin the logic/timing simulation.

In combination with a modified logic/timing simulation in which the testof the time behavior for each inserted, imaginary flip-flop IFF (or apart of the flip-flop IFF) is deactivated in a suitable way, a completetest of the signal-time behavior in the circuit can thus take place fora clocked circuit with asynchronous signals. All other undefinedstatusses to be detected, can be reliably acquired, as follows from FIG.8.

FIG. 8 shows a block circuit diagram of a circuit with a faultydimensioning of the logic DL acting a delay element that, for example,can follow at the output S_(out) of FIG. 5. The faulty dimensioning ofthe logic DL acting a delay element effects a violation of the setuptime of the following flip-flop FF_(out).

FIG. 10 shows an illustration of the signal-time curves of the criticalsignals according to FIG. 8, in which the time t_(LOGIK) represents thedelay time of the logic DL. According to FIG. 10, setup/hold timeviolations can likewise occur at the input of the flip-flop FF_(out)given poor dimensioning of the logic DL. According to FIG. 8, an inputflip-flop FFin and an output flip-flop FFout are clocked with the sameclock signal CLK. An input signal S_(in) is set to “1” with a leadingedge of the clock signal CLK and is again set to “0” with the nextleading clock edge. This signal S1 is supplied to the logic circuit DLthat is located between the input flip-flop FFin and the outputflip-flop FFout. Due to the gate running times of the logic DL, a timedelay of the signal arises that can lead to a case as shown in FIG. 10given poor dimensioning of the circuit. According to FIG. 10, theleading edge of the signal S2 delayed by the delay time t_(logic) of thelogic circuit DL coincides with the leading edge of the clock signalCLK, resulting in a setup time violation. Due to the lack of anadequately stable input signal at the input terminal D of the outputflip-flop FFout, an unknown status, which derives from theaforementioned metastable status and the undefined status, is obtainedfor an output signal Sout at the output terminal Q of the flip-flopFFout.

Such unwanted statusses can continue to be detected and localized in thelogic/timing simulation, in which a synchronization module for a markedasynchronous signal is merely inserted with the inventive method and thetest for setup/hold time violation is selectively deactivated.

FIG. 7 shows another exemplary embodiment of a flip-flop IFF to beinserted in the network list. The imaginary flip-flop or, respectively,synchronization module is again composed of a flip-flop FF2 and aflip-flop FF3, In this module, an inverter INV, however, is additionallyinserted that generates the clock signal {overscore (CLK)} by invertingthe clock signal CLK supplied to the flip-flop FF2. As a result, thesignal S4 output at the flip-flop 3 is already ready after one clockcycle.

The present invention has been described only on the basis of clockedflip-flops that are set with the leading edge. However, flip-flops canalso be employed that are set with the trailing edge, or a systemcombining both leading and trailing edge flip-flops may be used.Further, the present invention is not limited to clocked flip-flops but,on the contrary, relates to all types of clocked circuit elements inwhich the above-described events for generating unknown statusses canoccur. In particular, the employment of two flip-flops for thesynchronization module inserted into the network list can be arbitrarilychanged, as long as it allows a synchronization of two asynchronoussignals with respect to its time behavior and—over and above this—asetup time violation can be designationally deactivated.

FIG. 11 shows a flowchart of the above-described inventive method. In astep S1, first, an arbitrary circuit for which an ASIC, a full-custom ICor a semi-custom IC, is to be fabricated is described with a hardwaredescription language. All asynchronous signals or signal lines arethereby already marked. In the step S2, for example, a logic simulationof the VHDL code produced in this way can be implemented, by which thepurely logical operations of the circuit are tested. A synthesis of thehardware description language or, of the VHDL code for producing anetwork list follows in step S3, in which a pre-defined synchronizationmodule is inserted into the network list at the marked signals. Aspecific timing simulation is implemented in step S4 on the basis ofthis modified network list of the initial circuit, in which the test ofsetup/hold time violations is selectively deactivated for each insertedsynchronization module or at least a part of this synchronizationmodule. All undefined signal-time behaviors still occurring in thesynchronous signal paths, i.e., unknown statusses following setup/holdtime violations, continue to be detected and displayed. A VHDL code ispreferably employed as the hardware description language in the presentinvention. However, all other hardware description languages can beemployed in the same way insofar as they allow a marking of asynchronoussignals or, signal lines. Likewise, all types of synthesis tools can beemployed with which a network list can be produced from a hardwaredescription language which permits the insertion of a synchronizationmodule given occurrence of a marking. In the same way, all types ofsimulators can be employed for the timing simulations with which theinserted synchronization module or at least a part of this module can beselectively deactivated in view of the testing of the time behavior.

FIG. 12 shows an apparatus for the implementation of the above-describedmethod. The apparatus is essentially composed of an input 1, a firstmemory 2 for storing the hardware description language (VHDL code) and asecond memory 3 for storing the second code produced in the synthesis,i.e. the network list. A marking mechanism 4 selectively marks allasynchronous signals or, respectively, signal lines found in thehardware description language, whereas a logic simulator 8 implements alogic simulation for testing the logic functions of the circuit on thebasis of the hardware description language. A synthesis mechanism 6implements a synthesis of the hardware description language (VHDL code)that is marked and deposited in the memory 2, resulting in a modifiednetwork list arises that is deposited in the memory 3. The network listdeposited in the memory 3 has the inserted synchronization modules. Alogic/timing simulator 7 implements a logic/timing simulation at thenetwork list stored in the memory 3, which is configured such that notest of setup/hold time violations is implemented in the synchronizationmodule or parts of this module. The results acquired by the logicsimulator and timing simulator are output via a display 5, and thecircuit element causing the time infraction is optionally co-displayed.The elements 1 through 8 are preferably connected to one another via abus structure 9. The synthesis mechanism 6, the timing simulator 7 andthe logic simulator can be realized by one or more CPUs (centralprocessing units) with appertaining memory units (ROMs).

The above-described method and apparatus are illustrative of theprinciples of the present invention. Numerous modifications andadaptations thereof will be readily apparent to those skilled in thisart without departing from the spirit and scope of the presentinvention.

1. A method for the synchronization of an asynchronous signal insynthesis and simulation of a clocked circuit, comprising the steps of:a) describing said clocked circuit with a first code in a hardwaredescription language; b) marking asynchronous signals of said clockedcircuit in said first code; c) synthesizing said first code forproducing a second code in a network list format, and inserting asynchronization module at every said marking; d) implementing a logic ortiming simulation at said second code for testing time behavior ofsignals in said clocked circuit, and selectively deactivating said testof said time behavior for each inserted synchronization module byadaptation in a simulation model of the appertaining synchronizationmodule; and e) displaying occurring, undefined signal-time behavior insaid clocked circuit.
 2. The method according to claim 1, comprising thefurther step of: providing a logic simulation at said first code fortesting a logic function of said clocked circuit.
 3. The methodaccording to claim 1, wherein said first code represents a hardwaredescription language and said second code represents a network list. 4.The method according to claim 3, wherein said hardware descriptionlanguage is a VHDL code.
 5. The method according to claim 1, whereinsaid step of inserting said synchronization module implemented in thesynthesis of said first code corresponds to inserting an imaginaryflip-flop.
 6. The method according to patent claim 5, wherein saidimaginary flip-flop comprises a first and second flip-flop that areclocked with the same clock.
 7. The method according to patent claim 5,wherein said imaginary flip-flop comprises a first and a secondflip-flop that are clocked with clocks inverted relative to one another.8. The method according to claim 6, further comprising the step ofselectively deactivating a test of signal-time behavior upon saidimplementation of said timing simulation only for said first flip-flop.9. The method according to claim 1, further comprising the step ofdisplaying a circuit element causing an undefined signal-time behaviorwhen said undefined signal-time behavior is displayed.
 10. An apparatusfor detecting undefined signal-time behavior in a clocked circuitcomprising: a) an input for a first code describing a clocked circuit ina hardware description language; b) a first memory for storing saidfirst code; c) a marking mechanism for marking asynchronous signals insaid first code; d) a synthesis mechanism that produces a second code ina network list format from said first code and stores this in a secondmemory, a synchronization module being inserted at every marking; e) atiming simulator that implements a timing simulation at said second codefor testing time behavior of signals of said clocked circuit, the testof the time behavior being selectively deactivated for each insertedsynchronization module by adaptation in a simulation model of anappertaining synchronization module; f) a display for displayingoccurring, undefined signal-time behavior; and g) a bus structure thatconnects said input, said first memory, said second memory, said markingmechanism, said display, said synthesis mechanism, and said timingsimulator to one another.
 11. The apparatus according to claim 10,further comprising a logic simulator that implements a logic simulationbased on said first code for testing logic behavior of said clockedcircuit.
 12. The apparatus according to claim 10, wherein said firstcode represents a hardware description language and said second coderepresents a network list.
 13. The apparatus according to patent claim12, wherein said hardware description language is a VHDL code.
 14. Theapparatus according to claim 10, wherein said synchronization modulecorresponds to an imaginary flip-flop.
 15. The apparatus according toclaim 14, wherein said imaginary flip-flop comprises a first and secondflip-flop that are clocked with a same clock signal.
 16. The apparatusaccording to claim 14, wherein said imaginary flip-flop comprises afirst and a second flip-flop that are clocked with clock signals (CLK,{overscore (CLK)}) inverted relative to one another.
 17. The apparatusaccording to claim 15, wherein said timing simulator operatesindependently of time behavior for said first flip-flop in theimplementation of said timing simulation.
 18. The apparatus according toclaim 10, wherein said display also displays a circuit element causingundefined signal-time behavior.
 19. The method according to claim 7,further comprising the step of selectively deactivating a test ofsignal-time behavior upon said implementation of said timing simulationonly for said first flip-flop.
 20. The apparatus according to claim 16,wherein said timing simulator operates independently of time behaviorfor said first flip-flop in the implementation of said timingsimulation.